1. Field of the Invention
The present invention is directed to the fabrication of bipolar transistors and more particularly, to improving the current gain of bipolar transistors at low temperatures.
2. Description of the Prior Art
The operation of semiconductor devices at low temperatures has been used traditionally as a tool for exploring device physics. In the past several years, however, increasing emphasis has been placed on using the low temperature environment to enhance the performance of integrated circuits. The principal driving force in this trend has been the silicon complementary metal oxide semiconductor (CMOS) technologies which has resulted in the design and manufacture of a supercomputer operational at liquid nitrogen (LN.sub.2) temperatures. The advantages of the low temperature environment for FET transistors are many, and include enhanced carrier mobility and reduced leakage currents.
Despite the advantages offered by low temperature operation of CMOS circuits, the high sensitivity of field effect transistor (FET) technologies to capacitive loading is undesirable. Because significant circuit loading is inevitable regardless of operating temperature, this inherent shortcoming of CMOS technologies will remain in the LN.sub.2 environment. Attempts at integrating CMOS technologies with bipolar technologies (BiCMOS) that are capable of efficiently driving high capacitance loads because of their high transconductance have been quite successful in recent years. At the chip level significant room temperature performance improvements have been reported over conventional CMOS technologies Operation of BiCMOS circuits at LN.sub.2 temperatures, however, has received very little attention. The primary reason for this is the well known degradation of bipolar transistor characteristics at reduced temperatures. The principal device parameter that has been studied over the years is the transistor current gain beta (.beta.), which is typically observed to decay exponentially with decreasing temperature. The beta degradation is commonly associated with the difference in apparent bandgap narrowing between the base and emitter regions. The result is that device gain is very small (or non-existent) at LN.sub.2 temperatures, thereby precluding any consideration of bipolar transistors in low temperature applications.
There have been two basic techniques proposed to reduce this degradation of beta at low temperatures. The first has been to severely reduce the emitter doping level in the device in order to reduce the amount of apparent bandgap narrowing in the emitter as disclosed by Woo et al., Optimazation of Bipolar Transistors for Low Temperature Operation, IEDM Tech. Dig. (1987). This method, though successful in producing usable beta at low temperatures, is not consistent with the design requirements for high performance applications, however, for charge storage and emitter resistance reasons. The second technique is to increase the base doping level in the device to reduce the difference in apparent bandgap narrowing between the emitter and base regions as disclosed by Tang, Heavy Doping Effects in PNP Bipolar Transistors, IEEE Trans. Elec. Dev. ED-27 (1980) and Stork et al., High Performance Operation of Silicon Bipolar Transistors of Liquid Nitrogen Temperature, IEDM Tech. Dig. (1987). The latter technique is more consistent with traditional scaling laws but is limited because of the inherent emitter base leakage that results from any radical increase in the base doping level. In addition, it is known that this technique is not efficient for improving the low temperature beta because any increase in the bandgap narrowing in the base region which is beneficial to beta, is partially offset by a decrease in the freeze-out activation energy in the base region, which is a disadvantage to beta.
Techniques for improving emitter efficiency and hence increasing gain of bipolar transistors operating at room temperatures are known in the art. One such technique is disclosed in U.S. Pat. No. 4,559,696 which teaches the formation of a wide gap emitter by an additional ion implant of material having a higher energy gap then silicon subsequent to or simultaneously with the n or p-type doping of the emitter. The additional ion implant creates a potential barrier for the flow of holes from the base to the emitter that is greater than the potential barrier for the flow of electrons from the emitter to the base. The materials disclosed for the additional ion implant are carbon and nitrogen. While emitter efficiency and gain are improved in conventional room temperature operation, there is a need for an efficient method from improving the current gain of bipolar transistors at low temperatures.